Integrated circuits composed of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become the workhorse of the semiconductor industry. These integrated circuits contain from two to several million MOSFETs fabricated on a common semiconductor body. An individual MOSFET comprises a pair of regions of one conductivity type which have been formed in a semiconductor body and which are spaced apart by an intermediate portion of the semiconductor body which is of the opposite semiconductor type. Current flow between electrodes attached to these two spaced apart regions is controlled by an electrode (gate) positioned at a top surface adjacent the intermediate region which is electrically insulated therefrom by a thin layer of silicon dioxide that is formed by oxidizing a surface layer of the intermediate region. In operation, a voltage applied to the gate of sufficient magnitude and polarity to invert the conductivity type of the intermediate region gives rise to a conductive channel between the two spaced regions in which current flows when a suitable voltage is established by electrode connections to the two spaced apart regions. The two spaced apart regions are usually identified as the source and drain of the field effect transistor. The intermediate region between the source and drain is usually identified as the channel region.
It is well known that unless suitable precautions are taken, unwanted, parasitic current can, and will, flow between various elements of the integrated circuit. Parasitic current can flow between the source and drain region. It may not be controlled by the gate potential. Parasitic current can also flow between the source and drain regions of adjacent but separate transistors, and again is not controlled by the potential applied to the gates of the various transistors.
If the integrated circuit is of the type known as a Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit, these parasitic currents can give rise to a phenomenon known as "Latchup", a condition in which a very large, potentially destructive parasitic current can flow between the most positive and most negative power supply terminals of the integrated circuit. In a CMOS integrated circuit, two types of transistors are formed, each having opposite conductivity type in the intermediate region between the source and drain regions of the two types of transistor. Transistors of one type are formed directly in the semiconductor body, and transistors of the other type are formed in a region known as a "well", which is of conductivity type opposite that of the semiconductor body, and which has been diffused into the semiconductor body.
Various methods are in common use to reduce the magnitude of, or in some cases completely suppress, the various parasitic currents which can flow in an integrated circuit. One such method is to diffuse into the surface region of the semiconductor body, exterior to the source, drain and channel regions, impurities which increase the impurity concentration of the exterior regions such that the conductivity type of same can not be easily inverted. Such a diffusion is known as a "channel stopper" or "chanstop" diffusion. In these regions, the potential required to invert the conductivity type of the surface of the semiconductor body is greater than such potential in the channel region of the transistor, and is usually designed to be greater than the maximum potential applied to the integrated circuit.
Another method of reducing or suppressing the various parasitic currents is to form in the region exterior to the channel region an oxide whose thickness is greater than the thickness of the oxide formed under the gate electrode in the intermediate or channel region of the transistor. Again, in these regions, the potential at the top surface of the thicker oxide required to invert the surface of the semiconductor body will be greater than such potential in the channel region of the transistor, and is usually designed to be greater than the maximum potential applied to the integrated circuit.
Often, these two methods are combined in the effort to reduce or suppress the parasitic currents. Other methods which have been applied include the use of trenches filled with insulating material which are fabricated so as to completely surround and isolate each transistor, and the use of a field-shield, which is a conducting electrode formed over the region exterior to the source, drain channel region of the transistor, and which is connected to the lowest power supply potential applied to the integrated circuit. Such methods of reducing or suppressing the parasitic currents are further discussed in textbooks such as "Silicon Processing for the VLSI Era, Volume II, page 66, S. Wolf".
All of the above methods incur some expense or limitations, including increased manufacturing cost, increased processing complexity, and reduced or impaired circuit performance.
A device which limits parasitic current which is of a completely different nature than those described above is the Silicon-On-Insulator (SOI) device. In this device, the end result is that each individual transistor is completely encased in a protective insulating material which completely surrounds the transistor, thus preventing any parasitic current flow between adjacent transistors through a common substrate. An additional benefit of the SOI structure is the reduced capacitance between the source or drain and the semiconductor body which results in improved performance of the transistor.
In one form of SOI, semiconductor films are deposited on an insulating substrate, islands of semiconductor film are defined, and the semiconductor film is completely removed from the region between the islands. This region is subsequently filled with an insulating material, and individual transistors are formed in the islands. Small sub-circuits consisting of a small number of transistors can also be formed in a given island of semiconductor material.
In another form of SOI, the starting material is a silicon semiconductor body on the surface of which isolated islands of silicon are formed by oxidizing the silicon surrounding and underneath the islands. This latter method is preferred in many cases because the starting material is semiconductor substrates which are of the same type as are being used for the manufacture of other types of integrated circuit, and also because the semiconductor properties of the resulting islands are superior to that of semiconductor islands formed in a film of semiconductor material formed on the surface of an insulating substrate.
One weakness of these SOI techniques is that the islands of semiconductor material are not connected to a reference potential of the power supply, such as either ground or the highest potential supplied by the power source. In the conventional methods of forming an integrated circuit, the semiconductor body, and in the case of CMOS integrated circuits, the "well" also, is connected to one of the power supply terminals. In previously describe forms of SOI, the semiconductor islands are not connected directly to a reference potential, but are left unconnected, or "floating". This leads to an effect known as the "floating body effect" (FBE). The deleterious effect of FBE on the performance of SOI integrated circuits is well known, and has been described for example, in the article "Floating-Body Effects in Partially Depleted SOI CMOS Circuits, Lu et al., IEEE Journal of Solid State Circuits, Vol. 32, No. 8, August 1997". The effects of the FBE on circuit performance include extra power consumption, degraded noise margin and stability of the circuits, and, in certain dynamic circuits, logic state errors. These effects arise in part because of capacitive coupling between the semiconductor island and adjacent signal carrying conductor lines. The effect of the FBE on individual transistor characteristics include degraded breakdown voltage, a lowering of the threshold voltage at high drain potential, and hysteresis and instability during dynamic operation.
Prior art solutions to this problem have included the introduction of additional layers of interconnection which allow the connection of each individual semiconductor island to an appropriate reference potential. This requires an increase in the size of the integrated circuit because of the area which must be devoted to the connection of each individual semiconductor island to the interconnection layer, and also can require an increase in the number of process steps required to fabricate the integrated circuit. Both of these lead to higher manufacturing cost, and the increase in size can lead to lower performance of the integrated circuit.
In another prior art solution to the problems caused by the Floating-Body Effect, the starting material is a silicon semiconductor body into which oxygen ions are deeply implanted. The silicon semiconductor body is then annealed at a sufficiently high temperature so that the implanted oxygen atoms interact with the silicon semiconductor body to form a layer of insulating silicon dioxide buried beneath a surface layer of semiconducting silicon. In one type of prior art SOI technology, islands of silicon can then be formed in this semiconductor body by masking the region where islands are to be formed with a suitable material such as silicon nitride, and then oxidizing the surface of the semiconductor body to form regions of silicon dioxide which extend from the surface down to meet the buried layer of silicon dioxide which was formed previously. This results in the formation of completely isolated islands of silicon.
A further variation of this technology is to control the final oxidation such that the oxidized regions extending down from the surface do not meet the underlying buried oxide layer, but leave a thin film of silicon connecting the bottoms of all the silicon islands. This form of SOI is referred to as Body-Contacted Silicon-On-Insulator (BC-SOI) and is described in an article entitled "1 Giga Bit SOI DRAM with Fully Bulk Compatible Process and Body-Contacted SOI MOSFET Structure", by Koh et al., Digest of Technical Papers, International Electron Device Meeting, 1997.
It is desirable to provide a method of fabricating Source/Drain-On-Insulator (S/DOI) devices which provides the advantages of SOI devices, while providing the ability to selectively incorporate this benefit into parts of the circuit, leaving other parts of the circuit using standard, conventional devices, thereby enhancing the performance of the circuitry, and which method can be incorporated into the existing CMOS and/or Bipolar process flow using the existing, conventional tool set. Further, since the insulator material is only beneath the sources and drains of the transistors, the method should provide a means of limiting, or eliminating, the Floating-Body Effect (FBE) in the SOI devices.